Tahir Ghani is an Intel Fellow and director of transistor technology and integration for the Technology and Manufacturing Group. He is currently leading the Pathfinding team responsible for transistor design and front-end processor integration for Intel’s 22nm CMOS logic technology node.
Tahir Ghani is an Intel Fellow and director of transistor technology and integration for the Technology and Manufacturing Group. He is currently leading the Pathfinding team responsible for transistor design and front-end processor integration for Intel’s 22nm CMOS logic technology node.
Since joining Intel in 1994, Ghani has played a key role in developing world-class CMOS logic technologies. He has led the research and development teams responsible for introducing some of the most important innovations in transistor technology and implementing these into mainstream CMOS manufacturing. Ghani co-led the team responsible for developing industry-first HiK/Metal Gate CMOS transistor technology for Intel’s 45nm technology node. Prior to that, he led the integration team which was responsible for developing industry-first uniaxially strained silicon transistors for Intel’s 90 CMOS node. Ghani and co-workers were the first to publish a novel epitaxial SiGe source drain transistor at IEDM 2003 which introduced high levels of strain for significant PMOS mobility enhancement. As a member of the 22nm CMOS Pathfinding team at Intel, Ghani is currently leading 22nm CMOS transistor technology research and development.
Ghani has received two Intel Achievement Awards. The first, awarded in 1996, was for his role in developing leading-edge 0.25um CMOS transistor technology. He received the second in 2003 for developing uniaxially strained silicon transistor technology for Intel’s 90nm logic technology node. He has published more than 30 technical papers, many of which have been presented at leading technical conferences.
Ghani received his B.S. in electrical engineering at the University of Engineering and Technology in Lahore, Pakistan in 1984 and his Ph.D. in electrical engineering at Stanford University in 1994. He is a Fellow of IEEE.