|High Performance Logic Technology Development in the post-ULSI Era|
Registration: Open to all.
Date: November 24, 1998
Time: 11:00 am
Venue: Centre for Solid State Physics, University of the Punjab, Quaid-e-Azam Campus, Lahore
The integrated circuit industry has demonstrated phenomenal growth in transistor density and performance during the last three decades. Ever since the introduction of 1st SRAM, DRAM and microprocessor products (all fabricated by Intel Corporation ~1970), the number of transistors has roughly doubled every 2 years and microprocessor clock frequency has increased from less than 5 MHz to over 500 MHz. Moreover, this has been achieved by keeping the overall system power dissipation at acceptably low levels. These improvements have primarily been driven by improvements in process and device technology with feature size reducing to <0.25um (1/400th of the thickness of human hair) on memory and microprocessor products currently available in the market. This talk will be divided into two parts. The first section will present the results from Intel’s next-generation microprocessor process technology generation. This technology demonstrates the highest transistor performance (i.e. highest drive current for a given off-state leakage) reported to date in the literature. Moreover, this high performance has been demonstrated at ultra-low energies, with energy-delay product appreciably below the published industry trends. An SRAM product with more than 100 million transistors has been developed as a yield learning vehicle with a frequency exceeding 1GHz. The 2nd part of the talk will focus on describing key bottlenecks which could limit further technology scaling during the next two decades. Alternate material options, which could delay the onset of some of the limitations, will be presented.
Dr. Tahir Ghani
Intel Research Team, Intel Corporation
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